NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 702

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

18.1.60
18.1.61
702
AECC — Advanced Error Capabilities and Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 158h
Default Value:
RES — Root Error Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 170h
Default Value:
31:27
31:9
26:4
5:1
4:0
Bit
Bit
Bit
6
0
8
7
6
5
3
2
1
0
Bad TLP Mask (BT) — R/WO.
0 = No mask
1 = Mask for bad TLP reception.
Reserved
Receiver Error Mask (RE) — R/WO.
0 = No mask
1 = Mask for receiver errors.
Reserved
ECRC Check Enable (ECE) — RO. ECRC is not supported.
ECRC Check Capable (ECC) — RO. ECRC is not supported.
ECRC Generation Enable (EGE) — RO. ECRC is not supported.
ECRC Generation Capable (EGC) — RO. ECRC is not supported.
First Error Pointer (FEP) — RO.
Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error
interrupt allocated.
Reserved
Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel
one error will be captured.
ERR_FATAL/NONFATAL Received (ENR) — R/WC.
0 = No error message received.
1 = Either a fatal or a non-fatal error message is received.
Multiple ERR_COR Received (MCR) — RO. For ICH7, only one error will be captured.
ERR_COR Received (CR) — R/WC.
0 = No error message received.
1 = A correctable error message is received.
00000000h
00000000h
–
–
15Bh
173h
PCI Express* Configuration Registers (Desktop and Mobile Only)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
RO
32 bits
R/WC, RO
32 bits
®
ICH7 Family Datasheet
®
ICH7, only