NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 209

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.20.6
5.20.6.1
Intel
®
ICH7 Family Datasheet
USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial
Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that
cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only ICH7-specific interrupt and error-reporting behavior is
documented in this section. The EHCI Interrupts Section must be read first, followed by
this section of the datasheet to fully comprehend the EHC interrupt and error-reporting
functionality.
Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer
• Master Abort and Target Abort responses from hub interface on EHC-initiated read
• The ICH7 may assert the interrupts which are based on the interrupt threshold as
• Since the ICH7 supports the 1024-element Frame List size, the Frame List Rollover
• The ICH7 delivers interrupts using PIRQH#.
• The ICH7 does not modify the CERR count on an Interrupt IN when the “Do
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
• The Host System Error status bit is set
• The DMA engines are halted after completing up to one more transaction on the
• If enabled (by the Host System Error Enable), then an interrupt is generated
• If the status is Master Abort, then the Received Master Abort bit in configuration
• If the status is Target Abort, then the Received Target Abort bit in configuration
• If enabled (by the SERR Enable bit in the function’s configuration space), then the
Error can not occur on the ICH7.
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
soon as the status for the last complete transaction in the interrupt interval has
been posted in the internal write buffers. The requirement in the Enhanced Host
Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the
status is written to memory) is met internally, even though the write may not be
seen on DMI before the interrupt is asserted.
interrupt occurs every 1024 milliseconds.
Complete-Split” execution criteria are not met.
not get set on a control-structure-fetch that fails the late-start test. If subsequent
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
USB interface
space is set
space is set
Signaled System Error bit in configuration bit is set.
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