NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 634

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Table 16-3. Native Audio Bus Master Control Registers (Sheet 2 of 2)
Note:
634
Internal reset as a result of D3
except the registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well
registers will not be reset by the D3
Core well registers and bits not reset by the D3
Resume well registers and bits will not be reset by the D3
Offset
• offset 2Ch
• offset 30h
• offset 34h – Codec Access Semaphore Register (CAS)
• offset 30h
54h
55h
56h
58h
5Ah
5Bh
60h
64h
65h
66h
68h
6Ah
6Bh
80h
Mnemonic
PI2_PICB
PI2_CIV
PI2_LVI
PI2_PIV
PI2_SR
PI2_CR
SPPICB
SPBAR
SPCIV
SPLVI
SPPIV
SPSR
SPCR
SDM
–
–
–
33h – bits [29,15,11:10,0] Global Status (GLOB_STA)
33h – bits [17:16] Global Status (GLOB_STA)
2Fh – bits 6:0 Global Control (GLOB_CNT)
PCM In 2 Current Index Value
PCM In 2 Last Valid Index
PCM In 2 Status
PCM In 2 Position in Current Buffer
PCM In 2 Prefetched Index Value
PCM In 2 Control
S/PDIF Buffer Descriptor List Base
Address
S/PDIF Current Index Value
S/PDIF Last Valid Index
S/PDIF Status
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
S/PDIF Control
SData_IN Map
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
HOT
to D0 transition will reset all the core well registers
HOT
Name
to D0 transition.
HOT
to D0 transition:
00000000h
HOT
Default
Intel
0001h
0000h
0001h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
to D0 transition:
®
ICH7 Family Datasheet
R/WC, RO
R/WC, RO
R/W, R/W
R/W, R/W
(special)
(special)
R/W, RO
Access
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO