NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 225

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.21.4
Table 5-51. Enable for SMBALERT#
Table 5-52. Enables for SMBus Slave Write and SMBus Host Events
Intel
®
ICH7 Family Datasheet
Interrupts / SMI#
The ICH7 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).
Table 5-52
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
Slave Write to
Wake/SMI#
Command
Slave Write to
SMLINK_SLAVE_S
MI Command
Any combination of
Host Status
Register [4:1]
asserted
SMBALERT#
asserted low
(always
reported in
Host Status
Register, Bit
5)
Event
Event
and
Table 5-53
(Host Control
I/O Register,
Offset 02h,
INTREN
Bit 0)
Register, Offset
X
X
1
INTREN (Host
Control I/O
02h, Bit 0)
specify how the various enable bits in the SMBus function
X
X
0
1
1
D31:F3:Offset
SMB_SMI_EN
Configuration
40h, Bit 1)
Register,
(Host
X
1
0
SMB_SMI_EN (Host
D31:F3:Offset 40h,
Configuration
Register,
Bit1)
X
X
X
0
1
Offset 11h, Bit 2)
(Slave Command
SMBALERT_DIS
I/O Register,
X
0
0
Wake generated when
asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when
in the S0 state
(SMBUS_SMI_STS)
None
Interrupt generated
Host SMI# generated
Wake generated
Slave SMI#
generated
(SMBUS_SMI_STS)
Interrupt
generated
Event
Result
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