NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 65

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Signal Description
Table 2-12. Power Management Interface Signals (Sheet 2 of 3)
Intel
®
ICH7 Family Datasheet
(Desktop Only)
(Desktop Only)
(Desktop Only)
Mobile Only) /
Mobile Only) /
(Desktop and
SUS_STAT# /
Mobile Only)/
SYS_RESET#
MCH_SYNC#
(Mobile/Ultra
(Mobile/Ultra
(Mobile/Ultra
Mobile Only)
VRMPWRGD
BM_BUSY#
STP_PCI#
LAN_RST#
CLKRUN#
RSMRST#
LPCPD#
SUSCLK
GPIO32
GPIO18
WAKE#
Name
GPIO0
Type
I/O
O
O
O
I
I
I
I
I
I
I
System Reset: This pin forces an internal reset after being
debounced. The ICH7 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before
forcing a reset on the system.
Resume Well Reset: This signal is used for resetting the resume
power plane logic.
LAN Reset: When asserted, the internal LAN controller will be put into
reset. This signal must be asserted for at least 10 ms after the resume
well power (VccSus3_3 in desktop and VccLAN3_3 and VccLAN1_05 in
mobile) is valid. When deasserted, this signal is an indication that the
resume (LAN for mobile) well power is stable.
NOTE: LAN_RST# should be tied to RSMRST#.
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.
MCH SYNC: This input is internally ANDed with the PWROK input.
Connect to the ICH_SYNC# output of (G)MCH.
Suspend Status: This signal is asserted by the ICH7 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC interface.
Suspend Clock: This clock is an output of the RTC generator circuit to
use by other chips for refresh clock.
VRM Power Good: This should be connected to be the processor’s
VRM Power Good signifying the VRM is stable. This signal is internally
ANDed with the PWROK input.
Bus Master Busy: This signal supports the C3 state. It provides an
indication that a bus master device is busy. When this signal is
asserted, the BM_STS bit will be set. If this signal goes active in a C3
state, it is treated as a break event.
NOTE: This signal is internally synchronized using the PCICLK and a
NOTE: In desktop configurations, this signal pin is a GPIO.
PCI Clock Run: This clock supports the PCI CLKRUN protocol. It
connects to peripherals that need to request clock restart or
prevention of clock stopping.
Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock. It is used to support PCI
CLKRUN# protocol. If this functionality is not needed, this signal can
be configured as a GPIO.
NOTE: Refered to as STPPCI# on Ultra Mobile.
two-stage synchronizer. It does not need to meet any
particular setup or hold time.
Description
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