NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 632
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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Table 16-2.
632
NOTE:
1.
2.
3.
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the
AC ’97 controller. Accesses to these registers do not cause the cycle to be forwarded
over the AC-link to the codec. S/W could access these registers as bytes, word, DWord
or qword quantities, but reads must not cross DWord boundaries.
In the case of the split codec implementation, accesses to the different codecs are
differentiated by the controller by using address offsets 00h
address offsets 80h
tertiary codec.
The Global Control (GLOB_CNT) (D30:F2:2Ch) and Global Status (GLOB_STA)
(D30:F2:30h) registers are aliased to the same global registers in the audio and
modem I/O space. Therefore a read/write to these registers in either audio or modem
I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC ’97 controller. The six
channels, PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their
own set of Bus Mastering registers. The following register descriptions apply to all six
channels. The register definition section titles use a generic “x_” in front of the register
to indicate that the register applies to all six channels. The naming prefix convention
used in
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
Intel
(Codec ID =00)
5Ah
7Ch
7Eh
Primary Offset
®
Software should not try to access reserved registers
Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of
configuration register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration
register 40h.
The tertiary offset is only available through the memory space defined by the MMBAR
register.
Table 16-3
ICH7 Audio Mixer Register Configuration (Sheet 2 of 2)
DAh
FCh
FEh
Secondary Offset
(Codec ID =01)
and in the register description I/O address is as follows:
–
FFh for the secondary codec and address offsets 100h
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
15Ah
17Ch
17Eh
(Codec ID =10)
Tertiary Offset
Vendor Reserved
Vendor ID1
Vendor ID2
NAMBAR Exposed Registers
–
7Fh for the primary codec,
Intel
®
(D30:F2)
ICH7 Family Datasheet
–
17Fh for the
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