NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 747

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.29
19.2.30
19.2.31
Intel
®
ICH7 Family Datasheet
RIRBSTS—RIRB Status Register
(Intel
Memory Address:HDBAR + 5Dh
Default Value:
RIRBSIZE—RIRB Size Register
(Intel
Memory Address:HDBAR + 5Eh
Default Value:
IC—Immediate Command Register
(Intel
Memory Address:HDBAR + 60h
Default Value:
31:0
7:3
7:4
3:2
1:0
Bit
Bit
Bit
2
1
0
Reserved.
Response Overrun Interrupt Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the
Reserved.
Response Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit to 1 when an interrupt has been generated after N number
RIRB Size Capability — RO. Hardwired to 0100b indicating that the ICH7 only supports
a RIRB size of 256 RIRB entries (2048B)
Reserved.
RIRB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B)
Immediate Command Write — R/W. The command to be sent to the codec via the
Immediate Command mechanism is written to this register. The command stored in this
register is sent out over the link during the next available frame after a 1 is written to
the ICB bit (HDBAR + 68h: bit 0)
®
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
incoming responses to memory before additional incoming responses overrun the
internal FIFO. When the overrun occurs, the hardware will drop the responses that
overrun the buffer. An interrupt may be generated if the Response Overrun
Interrupt Control bit is set. Note that this status bit is set even if an interrupt is not
enabled for this event.
of Responses are sent to the RIRB buffer OR when an empty Response slot is
encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit
is set even if an interrupt is not enabled for this event.
00h
42h
00000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/WC
8 bits
RO
8 bits
R/W
32 bits
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