NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 298
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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7.1.55
298
BUC—Backed Up Control Register
Offset Address: 3414–3414h
Default Value:
All bits in this register are in the RTC well and only cleared by RTCRST#.
(Desktop
(Mobile/
Mobile
Only)
Only)
Ultra
7:3
Bit
2
1
1
0
Reserved
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by
RSMRST#, but not PLTRST# nor CF9h writes.
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and
PATA Reset State (PRS) — R/W.
0 = Disabled.
1 = The reset state of the PATA pins will be driven/tri-state.
Reserved
Top Swap (TS) — R/W.
0 = Intel
1 = ICH7 will invert A16 for cycles going to the BIOS space (but not the feature
If the ICH7 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then
this bit cannot be cleared by software. The strap jumper should be removed and the
system rebooted.
INIT3_3V# will go inactive with the same timings as the other processor I/F
signals (hold time after CPURST# inactive).
space) in the FWH.
0000000xb (Desktop Only)
0000001xb (Mobile/Ultra Mobile Only)
®
ICH7 will not invert A16.
Description
Attribute:
Size:
Chipset Configuration Registers
Intel
®
ICH7 Family Datasheet
R/W
8-bit
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