NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 416

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

10.7.2
Note:
10.7.3
416
NMI_EN—NMI Enable (and Real Time Clock Index)
Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
The RTC Index field is write-only for normal operation. This field can only be read in Alt-
Access Mode. Note, however, that this register is aliased to Port 74h (documented in),
and all bits are readable at that address.
PORT92—Fast A20 and Init Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bits
6:0
7:2
Bit
Bit
7
1
0
2
1
0
NMI Enable (NMI_EN) — R/W (special).
0 = Enable NMI sources.
1 = Disable All NMI sources.
Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to
the RTC to select which register or CMOS RAM address is being accessed.
Reserved
Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE
input signal to generate A20M# to the processor.
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the Intel
INIT# active for 16 PCI clocks.
PCI SERR# Enable (PCI_SERR_EN) — R/W.
0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable (SPKR_DAT_EN) — R/W.
0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.
0 = Disable
1 = Enable
70h
80h
No
92h
00h
No
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W (special)
8-bit
Core
R/W
8-bit
Core
®
ICH7 Family Datasheet
®
ICH7 will force