NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 421

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH7 Family Datasheet
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one
Bit
4
3
2
1
0
RTC clock period may not be detected by the ICH7.
System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
1 = ICH7 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to
NOTE: This bit is also reset by RSMRST# and CF9h resets.
CPU Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the
NOTES:
1.
2.
Minimum SLP_S4# Assertion Width Violation Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some
CPU Power Failure (CPUPWR_FLR) — R/WC.
0 = Software (typically BIOS) clears this bit by writing a 0 to it.
1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while the
NOTE: VRMPWRGD is sampled using the RTC clock. Therefore, low times that are less
PWROK Failure (PWROK_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1
NOTE: See
NOTE: In the case of true PWROK failure, PWROK will go low first before the
read this bit and clear it, if it is set.
system is in an S0 or S1 state.
programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset
A4h:bits 5:4). The ICH7 begins the timer when SLP_S4# is asserted during S4/S5
entry, or when the RSMRST# input is deasserted during G3 exit. Note that this bit
is functional regardless of the value in the SLP_S4# Assertion Stretch Enable
(D31:F0:Offset A4h:bit 3).
system was in an S0 or S1 state.
state.
state. The bit will be cleared only by software by writing a 1 to this bit or when the
system goes to a G3 state.
This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the
shutdown and reboot associated with the CPUTHRMTRIP# event.
The CF9h reset in the description refers to CF9h type core well reset which
includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO Timeout.
This type of reset will clear CTS bit.
cases before the default value is readable.
than one RTC clock period may not be detected by the ICH7.
VRMPWRGD.
Chapter 5.14.11.3
for more details about the PWROK pin functionality.
Description
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