NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 499

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.18
12.1.19
12.1.20
12.1.21
Note:
Intel
®
ICH7 Family Datasheet
CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h
Default Value:
INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch
Default Value:
INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh
Default Value:
IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2)
Address Offset: Primary:
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
7:0
7:0
Bit
Bit
7:0
Bit
Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is
80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in
configuration space indicates that the SATA function and PATA functions are combined
(values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE
mode (value of 01).
Interrupt Line — R/W. This field is used to communicate to software the interrupt line
that the interrupt pin is connected to.
Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config
Registers:Offset 3100h:
bits 11:8).
80h
00h
See Register Description
Secondary: 42h
0000h
40h
–
–
41h
43h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W
8 bits
RO
8 bits
R/W
16 bits
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