NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 507
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.28
12.1.29
12.1.30
Intel
®
ICH7 Family Datasheet
PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)
Address Offset: 74h
Default Value:
MSICI—Message Signaled Interrupt Capability
Identification (SATA–D31:F2)
Address Offset: 80h
Default Value:
MSIMC—Message Signaled Interrupt Message Control
(SATA–D31:F2)
Address Offset: 82h
Default Value:
14:9
15:8
15:8
Bits
Bits
Bits
7:2
1:0
7:0
15
8
7
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller.
Reserved
PME Enable (PMEE) — R/W.
0 = Disable.
1 = Enable. SATA controller generates PME# form D3
Reserved
Power State (PS) — R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
11 = D3
When in the D3
and memory spaces are not. Additionally, interrupts are blocked.
Next Pointer (NEXT): Indicates the next item in the list is the PCI power management
pointer.
Capability ID (CID): Capabilities ID indicates MSI.
Reserved
64 Bit Address Capable (C64): Capable of generating a 32-bit message only.
HOT
0000h
7005h
0000h
state
–
–
–
HOT
75h
81h
83h
state, the controller’s configuration space is available, but the I/O
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
HOT
on a wake event.
RO, R/W, R/WC
16 bits
RO
16 bits
R/W, RO
16 bits
507
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