NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 473

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

UHCI Controllers Registers
11.1.9
11.1.10
Intel
®
ICH7 Family Datasheet
MLT—Master Latency Timer Register
(USB—D29:F0/F1/F2/F3)
Address Offset: 0Dh
Default Value:
HEADTYP—Header Type Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
For functions 1, 2, and 3, this register is hardwired to 00h. For function 0, bit 7 is
determined by the values in the USB Function Disable bits (11:8 of the Function Disable
register Chipset Config Registers:Offset 3418h).
7:0
6:0
Bit
Bit
7
Master Latency Timer (MLT) — RO. The USB controller is implemented internal to the
Intel
Master Latency Timer.
Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
Since the upper functions in this device can be individually hidden, this bit is based on
the function-disable bits in Chipset Config Space: Offset 3418h as follows:
Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration
layout.
D29:F7_Disa
ble (bit 15)
®
0b
ICH7 and not arbitrated as a PCI device. Therefore the device does not require a
X
X
X
1
00h
0Eh
FN 0: 80h
FN 1: 00h
FN 2: 00h
FN 3: 00h
D29:F3_Disa
ble (bit 11)
0b
X
X
X
1
D29:F2_Disa
ble (bit10)
Description
Description
0b
Attribute:
Size:
X
X
X
1
Attribute:
Size:
D29:F1_Disa
ble (bit 9)
0b
X
X
X
1
RO
8 bits
RO
8 bits
Multi-Function
Device (this
bit)
1
1
1
1
0
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