NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 196

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

5.17.4.2.4
5.17.4.3
5.17.5
5.17.6
Note:
Note:
196
Non-AHCI Mode PME# Generation
When in non-AHCI mode (legacy mode) of operation, the SATA controller does not
generate PME#. This includes attach events (since the port must be disabled), or
interlock switch events (via the SATAGP pins).
SMI Trapping (APM)
Device 31:Function2:Offset C0h (see
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0
1F7h, 3F6h, 170
these addresses, accesses to one of these ranges with the appropriate bit set causes
the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated.
If an access to the Bus-Master IDE registers occurs while trapping is enabled for the
device being accessed, then the register is updated, an SMI# is generated, and the
device activity status bits
occurred.
SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port. The
SATALED# is an active-low open-collector output. When SATALED# is low, the LED
should be active. When SATALED# is high, the LED should be inactive.
AHCI Operation (Intel
The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a
programming interface for SATA host controllers developed thru a joint industry effort
(AHCI not available on all ICH7 components; see
transactions between the SATA controller and software and enables advanced
performance and usability with SATA. Platforms supporting AHCI may take advantage
of performance features such as no master/slave designation for SATA devices—each
device is treated as a master—and hardware assisted native command queuing. AHCI
also provides usability enhancements such as Hot-Plug. AHCI requires appropriate
software support (e.g., an AHCI driver) and for some features, hardware support in the
SATA device or additional platform hardware.
The ICH7 supports all of the mandatory features of the Serial ATA Advanced Host
Controller Interface Specification, Revision 1.0 and many optional features, such as
hardware assisted native command queuing, aggressive power management, LED
indicator support, and Hot-Plug thru the use of interlock switch support (additional
platform hardware and software may be required depending upon the implementation).
For reliable device removal notification while in AHCI operation without the use of
interlock switches (surprise removal), interface power management should be disabled
for the associated port. See Section 7.3.1 of the AHCI Specification for more
information.
When there are more than two PRD entries for a PIO data transfer that spans multiple
DATA FISes, the ICH7 does not support intermediate PRD entries that are less than 144
Words in size when the ICH7 is operating in AHCI mode at 1.5 Gb/s.
–
177h, and 376h). If the SATA controller is in legacy mode and is using
(Section
®
12.1.41) are updated indicating that a trap
ICH7R, ICH7DH, and Mobile Only)
Section
12.1.40) contain control for generating
Section
1.2). AHCI defines
Intel
®
ICH7 Family Datasheet
Functional Description
–