NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 425

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.1.5
Intel
®
ICH7 Family Datasheet
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile/Ultra Mobile Only)
Offset Address: AAh
Default Value:
Lockable:
Power Well:
This register is used to enable C-state related modes.
7:4
3:2
1:0
Bit
Reserved
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the Intel
ICH7-M/ICH7-U waits for from the deassertion of DPRSLPVR to the deassertion of
STP_CPU#. This provides a programmable time for the processor’s voltage to stabilize
when exiting from a C4 state. This changes the value for t266.
DPSLP-TO-SLP — R/W. This field selects the DPSLP# deassertion to CPU_SLP#
deassertion time (t270). Normally this value is determined by the
CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,
then the values in this register have higher priority. It is software’s responsibility to
program these fields in a consistent manner.
Bits
00b
01b
10b
11b
Bits
00b
01b
10b
11b
00h
No
Core
t266
95 µs
22 µs
34 µs
t270
Use value in CPU_PLL_LOCK_TIME field (default is 30 µs)
20 µs
15 µs (Recommended Value)
10 µs
min
t266
101 µs
28 µs
40 µs
max
Description
Comment
Default
Value used for “Fast” VRMs
Recommended Value
Reserved
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
®
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