NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 596

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

14.2.12
.
14.2.13
Note:
596
AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Dh
Default Value:
Lockable:
SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 0Eh
Default Value:
This register is in the resume well and is reset by RSMRST#.
This register is only applicable in the TCO compatible mode.
7:2
7:3
Bit
Bit
1
0
2
1
0
Reserved
Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable.
1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as
Automatically Append CRC (AAC) — R/W.
0 = ICH7 will Not automatically append the CRC.
1 = The ICH7 will automatically append the CRC. This bit must not be changed during
Reserved
SMLINK_CLK_CTL — R/W.
0 = Intel
1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state
SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLINK1 pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLINK0 pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
opposed to a single register. This enables the block commands to transfer or receive
up to 32-bytes before the Intel
SMBus transactions or undetermined behavior will result. It should be programmed
only once during the lifetime of the function.
logic would otherwise indicate for the SMLINK0 pin.
of the pin. (Default)
®
00h
No
See below
ICH7 will drive the SMLINK0 pin low, independent of what the other SMLINK
®
ICH7 generates an interrupt.
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
Intel
R/W
8 bits
Resume
R/W, RO
8 bits
®
ICH7 Family Datasheet