NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 311

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.17
8.1.18
8.1.19
8.1.20
Intel
®
ICH7 Family Datasheet
INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Dh
Default Value:
MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Eh
Default Value:
MAX_LAT — Maximum Latency Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Fh
Default Value:
CAP_ID — Capability Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: DCh
Default Value:
7:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s
interrupt request is connected to PIRQA#. However, in the Intel
when the LAN controller interrupt is generated PIRQE# will go active, not PIRQA#. Note
that if the PIRQE# signal is used as a GPI, the external visibility will be lost (though
PIRQE# will still go active internally).
Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in
increments of 0.25 μs) that the LAN controller needs to retain ownership of the PCI bus
when it initiates a transaction.
Maximum Latency (MAX_LAT) — RO. This field defines how often (in increments of
0.25 μs) the LAN controller needs to access the PCI bus.
Capability ID (CAP_ID)
integrated LAN controller supports PCI power management.
01h
08h
38h
01h
—
RO. Hardwired to 01h to indicate that the Intel
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
®
ICH7 implementation,
®
ICH7’s
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