NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 639

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.2.7
Intel
®
ICH7 Family Datasheet
x_CR—Control Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit
read from the address offset 08h. Software can also read this register individually by
doing a single, 8-bit read to offset 0Bh. Reads across DWord boundaries are not
supported.
7:5
Bit
4
3
2
1
0
Reserved.
Interrupt on Completion Enable (IOCE) — R/W. This bit controls whether or not an
interrupt occurs when a buffer completes with the IOC bit set in its descriptor.
0 = Disable. Interrupt will not occur.
1 = Enable.
FIFO Error Interrupt Enable (FEIE) — R/W. This bit controls whether the
occurrence of a FIFO error will cause an interrupt or not.
0 = Disable. Bit 4 in the Status register will be set, but the interrupt will not occur.
1 = Enable. Interrupt will occur.
Last Valid Buffer Interrupt Enable (LVBIE) — R/W. This bit controls whether the
completion of the last valid buffer will cause an interrupt or not.
0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.
1 = Enable.
Reset Registers (RR) — R/W (special).
0 = Removes reset condition.
1 = Contents of all Bus master related registers to be reset, except the interrupt
Run/Pause Bus Master (RPBM) — R/W.
0 = Pause bus master operation. This results in all state information being retained
1 = Run. Bus master operation starts.
enable bits (bit 4,3,2 of this register). Software needs to set this bit but need not
clear it since the bit is self clearing. This bit must be set only when the Run/Pause
bit (D30:F2:2Bh, bit 0) is cleared. Setting it when the Run bit is set will cause
undefined consequences.
(i.e., master mode operation can be stopped and then resumed).
NABMBAR + 0Bh (PICR),
NABMBAR + 1Bh (POCR),
NABMBAR + 2Bh (MCCR)
MBBAR + 4Bh (MC2CR)
MBBAR + 5Bh (PI2CR)
MBBAR + 6Bh (SPCR)
00h
No
Description
Attribute:
Size:
Power Well:
R/W, R/W (special)
8 bits
Core
639