NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 295

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.52
7.1.53
Intel
®
ICH7 Family Datasheet
RC—RTC Configuration Register
Offset Address: 3400–3403h
Default Value:
HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h
Default Value:
31:5
31:8
1:0
6:2
1:0
Bit
Bit
4
3
2
7
Reserved
Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be
Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be
Upper 128 Byte Enable (UE) — R/W.
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
Reserved
Reserved
Address Enable (AE) — R/W.
0 = Address disabled.
1 = The Intel
Reserved
Address Select (AS) — R/W. This field selects 1 of 4 possible memory address
ranges for the High Precision Timer functionality. The encodings are:
00 = FED0_0000h – FED0_03FFh
01 = FED0_1000h – FED0_13FFh
10 = FED0_2000h – FED0_23FFh
11 = FED0_3000h – FED0_33FFh
accessed. Writes will be dropped and reads will not return valid data. This bit is
reset on system reset.
accessed. Writes will be dropped and reads will not return valid data. Bit reset on
system reset.
selected by bits 1:0 below.
00000000h
00000000h
®
ICH7 will decode the High Precision Timer memory address range
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, R/WLO
32-bit
R/W
32-bit
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