NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 338

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

8.3.15
338
STA—Status Register
(ASF Controller—B1:D8:F0)
Offset Address: F2h
Default Value:
This register gives status indication about several aspects of ASF.
5:4
Bit
7
6
3
2
1
0
EEPROM Loading (STA_LOAD) — R/W. EEPROM defaults are in the process of being
loaded when this bit is a 1.
EEPROM Invalid Checksum Indication (STA_ICRC) — R/W. This bit should be read
only after the EEC_LOAD bit is a 0.
0 = Valid
1 = Invalid checksum detected for ASF portion of the EEPROM.
Reserved
Power Cycle Status (STA_CYCLE) — R/W.
0 = Software clears this bit by writing a 1.
1 = This bit is set when a Power Cycle operation has been issued.
Power Down Status (STA_DOWN) — R/W.
0 = Software clears this bit by writing a 1
1 = This bit is set when a Power Down operation has been issued.
Power Up Status (STA_UP) — R/W.
0 = Software clears this bit by writing a 1
1 = This bit is set when a Power Up operation has been issued.
System Reset Status (STA_RST) — R/W.
0 = Software clears this bit by writing a 1
1 = This bit is set when a System Reset operation has been issued.
40h
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Description
Attribute:
Size:
Intel
R/W
8 bits
®
ICH7 Family Datasheet