NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 77
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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Signal Description
Table 2-23. Functional Strap Definitions (Sheet 2 of 3)
Intel
®
ICH7 Family Datasheet
(Mobile/Ultra
Mobile Only)
and Mobile
INTVRMEN
and Mobile
DPRSLPVR
GPIO17#,
EE_DOUT
(Desktop
(Desktop
(Desktop
GNT5# /
GNT4# /
GPIO48
GPIO16
GPIO25
GNT2#
GNT3#
Signal
Only) /
Only)
Only)
VccSus1_05
Destination
DMI AC/DC
Integrated
Boot BIOS
Top-Block
Reserved
Reserved
Selection
Reserved
Selection
(Desktop
Override
Coupling
Enable/
Disable
Usage
Swap
Only)
VRM
Rising Edge of
Rising Edge of
Rising Edge of
RSMRST#
Sampled
PWROK
PWROK
Always
When
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
The signal has a weak internal pull-up. If the signal
is sampled low, this indicates that the system is
strapped to the “top-block swap” mode (Intel
ICH7 inverts A16 for all cycles targeting FWH BIOS
space). The status of this strap is readable via the
Top Swap bit (Chipset Configuration
Registers:Offset 3414h:bit 0). Note that software
will not be able to clear the Top-Swap bit until the
system is rebooted without GNT3# being pulled
down.
This field determines the destination of accesses to
the BIOS memory range. Signals have weak
internal pull-ups. Also controllable via Boot BIOS
Destination bit (Chipset Configuration
Registers:Offset 3410h:bit 11:10)
(GNT5# is MSB)
01 = SPI (Desktop and Mobile Only)
10 = PCI
11 = LPC
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
This signal has a weak internal pull-up.The internal
pull-up is disabled within 100 ms after RSMRST#
deasserts.
If the signal is sampled high, the DMI interface is strapped
to operate in DC coupled mode (No coupling capacitors
are required on DMI differential pairs).
If the signal is sampled low, the DMI interface is strapped
to operate in AC coupled mode (Coupling capacitors are
required on DMI differential pairs).
NOTE: Board designer must ensure that DMI
NOTE: The signal must be held low at least 2 us after
Enables integrated VccSus1_05 VRM when sampled
high.
implementation matches the strap selection.
RSMRST# deassertion to enable AC coupled
mode.
Comment
®
77
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