NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 591

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
14.2.2
Note:
Intel
®
ICH7 Family Datasheet
HST_CNT—Host Control Register (SMBUS—D31:F3)
Register Offset: SMBASE + 02h
Default Value:
A read to this register will clear the byte pointer of the 32-byte buffer.
Bit
7
6
5
PEC_EN — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase
1 = Causes the host controller to perform the SMBus transaction with the Packet Error
START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All
LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h,
appended.
Checking phase appended. For writes, the value of the PEC byte is transferred from
the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit
must be written prior to the write in which the START bit is set.
register (offset 00h) can be used to identify when the Intel
command.
registers should be setup prior to writing a 1 to this bit position.
received for the block. This causes the ICH7 to send a NACK (instead of an ACK)
after receiving the last byte.
bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is
set, the LAST_BYTE bit cannot be cleared. This prevents the ICH7 from running
some of the SMBus commands (Block Read/Write, I
00h
Description
Attribute:
Size:
2
C Read, Block I
R/W, WO
8-bits
®
ICH7 has finished the
2
C Write).
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