NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 267

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.6
7.1.7
Intel
®
ICH7 Family Datasheet
V0CAP—Virtual Channel 0 Resource Capability Register
Offset Address: 0010–0013h
Default Value:
V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h
Default Value:
31:24
22:16
30:27
26:24
23:20
19:17
13:8
15:8
7:0
7:1
Bit
Bit
23
15
14
31
16
0
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table
since the arbitration is fixed.
Reserved
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and
therefore this field is not used.
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not
just advanced packet switching transactions.
Reserved
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed
port arbitration.
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and
cannot be disabled.
Reserved
Virtual Channel Identifier (ID) — RO. This field indicates the ID to use for this virtual
channel.
Reserved
Port Arbitration Select (PAS) — R/W. This field indicates which port table is being
programmed. The root complex takes no action on this setting since the arbitration is
fixed and there is no arbitration table.
Load Port Arbitration Table (LAT) — RO. The root complex does not implement an
arbitration table for this virtual channel.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates
which transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
00000001h
800000FFh
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
32-bit
R/W, RO
32-bit
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