NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 593

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
14.2.3
14.2.4
14.2.5
14.2.6
Intel
®
ICH7 Family Datasheet
HST_CMD—Host Command Register (SMBUS—D31:F3)
Register Offset: SMBASE + 03h
Default Value:
XMIT_SLVA—Transmit Slave Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 04h
Default Value:
This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
HST_D0—Host Data 0 Register (SMBUS—D31:F3)
Register Offset: SMBASE + 05h
Default Value:
HST_D1—Host Data 1 Register (SMBUS—D31:F3)
Register Offset: SMBASE + 06h
Default Value:
7:1
7:0
7:0
7:0
Bit
Bit
Bit
Bit
0
Address — R/W. This field provides a 7-bit address of the targeted slave.
RW — R/W. Direction of the host transfer.
0 = Write
1 = Read
Data0/Count — R/W. This field contains the 8-bit data sent in the DATA0 field of the
SMBus protocol. For block write commands, this register reflects the number of bytes to
transfer. This register should be programmed to a value between 1 and 32 for block
counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host
controller does not check or log invalid block counts.
Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus
protocol during the execution of any command.
This 8-bit field is transmitted by the host controller in the command field of the SMBus
protocol during the execution of any command.
00h
00h
00h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W
8 bits
R/W
8 bits
R/W
8 bits
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