NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 664
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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Note:
Note:
17.2.10
Note:
664
On reads from a codec, the controller will give the codec a maximum of four frames to
respond, after which if no response is received, it will return a dummy read completion
to the processor (with all F’s on the data) and also set the Read Completion Status bit
in the Global Status Register.
Reads across DWord boundaries are not supported.
CAS—Codec Access Semaphore Register
(Modem—D30:F3)
I/O Address:
Default Value:
Lockable:
Reads across DWord boundaries are not supported.
7:1
Bit
Bit
2
1
0
0
Modem Out Interrupt (MOINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the modem out channel interrupts status bits has been set.
Modem In Interrupt (MIINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the modem in channel interrupts status bits has been set.
GPI Status Change Interrupt (GSCI) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set.
NOTE: This bit is not affected by AC ‘97 Audio Modem function D3
Reserved
Codec Access Semaphore (CAS) — R/W (special). This bit is read by software to
check whether a codec access is currently in progress.
0 = No access in progress.
1 = The act of reading this register sets this bit to 1. The driver that read this bit can
This indicates that one of the GPI’s changed state, and that the new values are
available in slot 12.
then perform an I/O access. Once the access is completed, hardware automatically
clears this bit.
NABMBAR + 44h
00h
No
AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
Description
Description
§
Attribute:
Size:
Power Well:
Intel
R/W (special)
8 bits
Core
®
ICH7 Family Datasheet
HOT
to D0 Reset.
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