NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 611

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NH82801GHM S L8YR

Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801GHM S L8YR

Lead Free Status / RoHS Status
Compliant
IDE Controller Registers (D31:F1)
15.1.23
15.1.24
Note:
Intel
®
ICH7 Family Datasheet
SDMA_CNT—Synchronous DMA Control Register
(IDE—D31:F1)
Address Offset: 48h
Default Value:
SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset: 4Ah
Default Value:
For FAST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to
for details.
(Desktop
Mobile
Mobile
15:14
13:12
11:10
Only)
(Ultra
Only)
and
7:4
3:2
9:8
7:6
Bit
Bit
1
1
0
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the Intel
Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 1.
Reserved
Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 0.
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the Intel
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH7.
Reserved
00h
0000h
4Bh
Description
®
Description
Attribute:
Size:
Attribute:
Size:
ICH7.
®
ICH7.
R/W
8 bits
R/W
16 bits
Section 5.16.4
611

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