NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 597

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
14.2.14
Note:
14.2.15
Note:
Intel
®
ICH7 Family Datasheet
SMBUS_PIN_CTL—SMBUS Pin Control Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 0Fh
Default Value:
This register is in the resume well and is reset by RSMRST#.
SLV_STS—Slave Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 10h
Default Value:
This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
7:3
7:1
Bit
Bit
2
1
0
0
Reserved
SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of
0 = Intel
SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent
on an external signal level. This pin returns the value on the SMBDATA pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMBCLK pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
Reserved
HOST_NOTIFY_STS — R/WC. The Intel
completely received a successful Host Notify Command on the SMLink pins. Software
reads this bit to determine that the source of the interrupt or SMI# was the reception of
the Host Notify Command. Software clears this bit after reading any information
needed from the Notify address and data registers by writing a 1 to this bit. Note that
the ICH7 will allow the Notify Address and Data registers to be over-written once this
bit has been cleared. When this bit is 1, the ICH7 will NACK the first byte (host address)
of any new “Host Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
the pin.
would otherwise indicate for the SMBCLK pin. (Default)
®
See below
00h
ICH7 drives the SMBCLK pin low, independent of what the other SMB logic
Description
Description
®
Attribute:
Size:
Attribute:
Size:
ICH7 sets this bit to a 1 when it has
R/W, RO
8 bits
R/WC
8 bits
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