NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 695
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.48
18.1.49
18.1.50
Intel
®
ICH7 Family Datasheet
VCH—Virtual Channel Capability Header Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 100h
Default Value:
VCAP2—Virtual Channel Capability 2 Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 108h
Default Value:
PVC—Port Virtual Channel Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 10Ch
Default Value:
31:20
19:16
31:24
15:0
23:0
15:4
3:1
Bit
Bit
Bit
0
Next Capability Offset (NCO) — RO. This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates that this is version 1 of the capability
structure by the PCI SIG.
Capability ID (CID) — RO. This field indicates that this is the Virtual Channel capability
item.
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present for
VC arbitration since it is fixed.
Reserved.
Reserved.
VC Arbitration Select (AS) — R/W. This field indicates which VC should be
programmed in the VC arbitration table. The root port takes no action on the setting of
this field since there is no arbitration table.
Load VC Arbitration Table (LAT) — R/W. This bit indicates that the table
programmed should be loaded into the VC arbitration table. This bit always returns 0
when read.
18010002h
00000001h
0000h
–
–
–
103h
10Bh
10Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
32 bits
RO
32 bits
R/W
16 bits
695
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