NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 627

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.15
T
16.1.16
16.1.17
Intel
®
ICH7 Family Datasheet
SID—Subsystem Identification Register (Audio—D30:F2)
Address Offset: 2Eh
Default Value:
Lockable:
The SID register, in combination with the Subsystem Vendor ID register (D30:F2:2Ch)
make it possible for the operating environment to distinguish one audio subsystem
from the other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3
CAP_PTR—Capabilities Pointer Register (Audio—D30:F2)
Address Offset: 34h
Default Value:
Lockable:
This register indicates the offset for the capability pointer.
INT_LN—Interrupt Line Register (Audio—D30:F2)
Address Offset: 3Ch
Default Value:
Lockable:
This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.
15:0
7:0
7:0
Bit
Bit
Bit
Subsystem ID — R/WO.
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer
offset is offset 50h
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel
to communicate to software the interrupt line that the interrupt pin is connected to.
0000h
No
50h
No
00h
No
–
2Fh
HOT
Description
Description
Description
to D0 transition.
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
RO
8 bits
Core
R/W
8 bits
Core
®
ICH7. It is used
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