NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 231

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
Note:
5.21.7.3
Note:
Table 5-58. Host Notify Format
Intel
®
ICH7 Family Datasheet
other words, if a Start
protocol), and the address matches the ICH7’s Slave Address, the ICH7 will still grab
the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start
Read sequence beginning at bit 20. Once again, if the Address matches the ICH7’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and
proceed with the Slave Read cycle.
An external microcontroller must not attempt to access the ICH7’s SMBus Slave logic
until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).
Format of Host Notify Command
The ICH7 tracks and responds to the standard Host Notify command as specified in the
System Management Bus (SMBus) Specification, Version 2.0. The host address for this
command is fixed to 0001000b. If the ICH7 already has data for a previously-received
host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address
byte of the protocol. This allows the host to communicate non-acceptance to the
master and retain the host notify address and data values for the previous cycle until
host software completely services the interrupt.
Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 5-58
17:11
27:20
36:29
8:2
Bit
10
18
19
28
37
38
1
9
Start
SMB Host Address — 7
bits
Write
ACK (or NACK)
Device Address – 7 bits
Unused — Always 0
ACK
Data Byte Low — 8 bits
ACK
Data Byte High — 8 bits
ACK
Stop
shows the Host Notify format.
Description
–
Address
–
Read occurs (which is invalid for SMBus Read or Write
External
Master
External
Master
External
Master
External
Master
External
Master
ICH7
External
Master
ICH7
External
Master
ICH7
External
Master
Intel
Driven By
®
ICH7
Always 0001_000
Always 0
ICH7 NACKs if HOST_NOTIFY_STS is 1
Indicates the address of the master;
loaded into the Notify Device Address
Register
7-bit-only address; this bit is inserted to
complete the byte
Loaded into the Notify Data Low Byte
Register
Loaded into the Notify Data High Byte
Register
Comment
–
Address
–
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