NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 301

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.57
Intel
®
ICH7 Family Datasheet
CG—Clock Gating (Mobile/Ultra Mobile Only)
Offset Address: 341C–341Fh
Default Value:
29:28
Bit
Bit
31
30
27
26
25
24
2
1
0
Serial ATA Disable (SAD) — R/W. Default is 0.
0 = The SATA controller is enabled.
1 = The SATA controller is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
Parallel ATA Disable (PAD) — R/W.
0 = The PATA controller is enabled. (Default)
1 = The PATA controller is disabled and its PCI configuration space is not accessible.
Reserved
Legacy (LPC) Dynamic Clock Gate Enable — R/W.
0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
PATA Dynamic Clock Gate Enable — R/W.
0 = PATA Dynamic Clock Gating is Disabled
1 = PATA Dynamic Clock Gating is Enabled
USB UHCI Dynamic Clock Gate Enable — R/W.
0 = USB UHCI Dynamic Clock Gating is Disabled
1 = USB UHCI Dynamic Clock Gating is Enabled
0 = Reserved
1 = Reserved
SATA Port 3 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 3 Dynamic Clock Gating is Disabled
1 = SATA Port 3 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
SATA Port 2 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 2 Dynamic Clock Gating is Disabled
1 = SATA Port 2 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
SATA Port 1 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 1 Dynamic Clock Gating is Disabled
1 = SATA Port 1 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
SATA Port 0 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 0 Dynamic Clock Gating is Disabled
1 = SATA Port 0 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
00000000h
Description
Description
Attribute:
Size:
R/W, RO
32-bit
301