NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 234

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

5.22.1
5.22.2
Note:
234
PCI Power Management
This Power Management section applies for all AC ’97 controller functions. After a
power management event is detected, the AC ’97 controller wakes the host system.
The following sections describe these events and the AC ’97 controller power states.
Device Power States
The AC ’97 controller supports D0 and D3 PCI Power Management states. The following
are notes regarding the AC ’97 controller implementation of the Device States:
AC-Link Overview
The ICH7 is an AC ’97 2.3 controller that communicates with companion codecs via a
digital serial link called the AC-link. All digital audio/modem streams and command/
status information is communicated over the AC-link.
The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and
output data streams, as well as control register accesses, employing a time division
multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through
individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing
and 12 incoming data streams, or slots. The architecture of the ICH7 AC-link allows a
maximum of three codecs to be connected.
of the AC-link for the ICH7. The AC-link consists of a five signal interface between the
ICH7 and codec(s).
The ICH7’s AC ‘97 controller shares the signal interface with the Intel High Definition
Audio controller. However, only one controller may be enabled at a time.
10. Once the interrupt status bits are set, they will cause PIRQB# if their respective
1. The AC ’97 controller hardware does not inherently consume any more power when
2. In the D0 state, all implemented AC ’97 controller features are enabled.
3. In D3 state, accesses to the AC ’97 controller memory-mapped or I/O range results
4. In D3 state, the AC ’97 controller interrupt will not assert for any reason. The
5. When the Device Power State field is written from D3
6. AC97 STS bit is set only when the audio or modem resume events were detected
7. GPIO Status change interrupt no longer has a direct path to the AC97 STS bit. This
8. Resume events on ACZ_SDIN[2:0] cause resume interrupt status bits to be set
9. Edge detect logic prevents the interrupts from being asserted in case the AC97
it is in the D0 state than it does in D3 state. However, software can halt the DMA
engine prior to entering these low power states such that the maximum power
consumption is reduced.
in master abort.
internal PME# signal is used to signal wake events, etc.
generated. See
and their respective PME enable bits were set.
causes a wake up event only if the modem controller was in D3
only if their respective controllers are not in D3.
controller is switched from D3 to D0 after a wake event.
enable bits were set. One of the audio or the modem drivers will handle the
interrupt.
Section 17.1
for general rules on the effects of this reset.
Figure 5-13
shows a three codec topology
HOT
Intel
to D0, an internal reset is
®
ICH7 Family Datasheet
Functional Description