NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 497

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.13
12.1.14
12.1.15
12.1.15.1
Intel
®
ICH7 Family Datasheet
SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1)
Address Offset: 1Ch
Default Value:
NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command
BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2)
Address Offset: 20h
Default Value:
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte IO space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
ABAR — AHCI Base Address Register
(SATA–D31:F2)
Non AHCI Capable (Intel
Address Offset: 24h–27h
Default Value:
31:16
31:16
15:2
15:4
31:0
3:1
Bit
Bit
Bit
1
0
0
Block.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (4
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (16
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Reserved
00000001h
00000001h
00000000h
–
–
23h
1Fh
®
ICH7 Feature Supported Components Only)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
R/W, RO
32 bits
RO
32 bits
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