NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 641
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Intel
®
ICH7 Family Datasheet
NOTE: Reads across DWord boundaries are not supported.
Bit
3
2
1
0
AC-LINK Shut Off (LSO) — R/W.
0 = Normal operation.
1 = Controller disables all outputs which will be pulled low by internal pull down
NOTE: This bit is not affected by AC ‘97 Audio Function D3
AC ’97 Warm Reset — R/W (special).
0 = Normal operation.
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset
NOTE: This bit is not affected by AC ‘97 Audio Function D3
AC ’97 Cold Reset# — R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry.
1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1.
NOTE: This bit is in the core well and is not affected by AC ‘97 Audio Function D3
GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of
any GPI causes an interrupt.
0 = Bit 0 of the Global Status register is set, but no interrupt is generated.
1 = The change in value of a GPI causes an interrupt and sets bit 0 of the Global Status
NOTE: This bit is not affected by AC ‘97 Audio Function D3
resistors.
will awaken a suspended codec without clearing its internal registers. If software
attempts to perform a warm reset while bit_clk is running, the write will be ignored
and the bit will not change. This bit is self-clearing (it remains set until the reset
completes and bit_clk is seen on the AC-link, after which it clears itself).
All data in the controller and the codec will be lost. Software needs to clear this bit
no sooner than the minimum number of ms have elapsed.
The value of this bit is retained after suspends; hence, if this bit is set to a 1 prior
to suspending, a cold reset is not generated automatically upon resuming.
register.
D0 reset.
Description
HOT
HOT
HOT
to D0 reset.
to D0 reset.
to D0 reset.
HOT
to
641
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