NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 151

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
Figure 5-7.
5.13.1.4
Table 5-23. NMI Sources
5.13.1.5
Note:
5.13.1.6
5.13.1.7
Intel
®
ICH7 Family Datasheet
Coprocessor Error Timing Diagram
If COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an
internal IRQ13, nor will the write to F0h generate IGNNE#.
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Table
Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#)
The ICH7 power management logic controls these active-low signals. Refer to
Section 5.14
CPU Sleep (CPUSLP#) is supported only on desktop platforms.
CPU Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. This signal represents a
logical AND of the ICH7’s PWROK and VRMPWRGD signals.
Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only)
This active-low signal controls the internal gating of the processor’s core clock. This
signal asserts before and deasserts after the STP_CPU# signal to effectively stop the
processor’s clock (internally) in the states in which STP_CPU# can be used to stop the
processor’s clock externally.
SERR# goes active (either internally,
externally via SERR# signal, or via
message from (G)MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
5-23.
I/O Write to F0h
Internal IRQ13
Cause of NMI
IGNNE#
for more information on the functionality of these signals.
FERR#
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
Comment
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