NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 588

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

14.1.14
14.2
Table 14-2. SMBus I/O Register Address Map
588
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value:
SMBus I/O Registers
SMB_BASE
7:3
+ Offset
0Ah–0Bh
Bit
2
1
0
0Ch
0Dh
00h
02h
03h
04h
05h
06h
07h
08h
09h
0Eh
Reserved
I
0 = SMBus behavior.
1 = The Intel
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
1 = Enable. The SMB Host controller interface is enabled to execute commands. The
2
C_EN — R/W.
formatting of some commands.
to
be enabled.
INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host
controller to interrupt or SMI#. Note that the SMB Host controller will not respond
to any new requests until all interrupt requests have been cleared.
HOST_BLOCK_DB
SMLINK_PIN_CTL
Section 5.21.4
Mnemonic
XMIT_SLVA
00h
RCV_SLVA
SLV_DATA
HST_CMD
HST_STS
HST_CNT
AUX_STS
AUX_CTL
HST_D0
HST_D1
PEC
®
ICH7 is enabled to communicate with I
(Interrupts / SMI#). This bit needs to be set for SMBALERT# to
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Packet Error Check
Receive Slave Address
Receive Slave Data
Auxiliary Status
Auxiliary Control
SMLink Pin Control (TCO
Compatible Mode)
Register Name
Description
Attribute:
Size:
SMBus Controller Registers (D31:F3)
2
C devices. This will change the
Intel
R/W
8 bits
description
Default
register
0000h
®
00h
00h
00h
00h
00h
00h
00h
00h
44h
00h
00h
See
ICH7 Family Datasheet
R/WC, RO,
R/WC, RO
R/W, WO
(special)
R/W, RO
Type
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO