NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 19

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

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Intel
®
13.2
SMBus Controller Registers (D31:F3) .................................................................... 583
14.1
14.2
ICH7 Family Datasheet
13.1.19PWR_CNTL_STS—Power Management Control/
13.1.20DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7) ...... 554
13.1.21NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F7) ................ 554
13.1.22DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F7) ......... 554
13.1.23USB_RELNUM—USB Release Number Register (USB EHCI—D29:F7) ............ 555
13.1.24FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F7) .............. 555
13.1.25PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F7) ............... 556
13.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extended
13.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended
13.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..... 559
13.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) .................... 560
Memory-Mapped I/O Registers .......................................................................... 561
13.2.1 Host Controller Capability Registers ........................................................ 561
13.2.2 Host Controller Operational Registers ...................................................... 564
13.2.3 USB 2.0-Based Debug Port Register ........................................................ 577
PCI Configuration Registers (SMBUS—D31:F3) .................................................... 583
14.1.1 VID—Vendor Identification Register (SMBUS—D31:F3) .............................. 583
14.1.2 DID—Device Identification Register (SMBUS—D31:F3) .............................. 584
14.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3) ................................. 584
14.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3) ....................................... 585
14.1.5 RID—Revision Identification Register (SMBUS—D31:F3) ............................ 585
14.1.6 PI—Programming Interface Register (SMBUS—D31:F3) ............................. 586
14.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3) ..................................... 586
14.1.8 BCC—Base Class Code Register (SMBUS—D31:F3).................................... 586
14.1.9 SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3) ................... 586
14.1.10SVID — Subsystem Vendor Identification Register (SMBUS—D31:F2/F4) ..... 587
14.1.11SID — Subsystem Identification Register (SMBUS—D31:F2/F4) .................. 587
14.1.12INT_LN—Interrupt Line Register (SMBUS—D31:F3)................................... 587
14.1.13INT_PN—Interrupt Pin Register (SMBUS—D31:F3) .................................... 587
14.1.14HOSTC—Host Configuration Register (SMBUS—D31:F3)............................. 588
SMBus I/O Registers ........................................................................................ 588
14.2.1 HST_STS—Host Status Register (SMBUS—D31:F3) ................................... 589
14.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3) .................................. 591
14.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3) ............................. 593
Status Register (USB EHCI—D29:F7) ...................................................... 553
Capability Register (USB EHCI—D29:F7).................................................. 556
Control / Status Register (USB EHCI—D29:F7) ......................................... 557
13.2.1.1 CAPLENGTH—Capability Registers Length Register....................... 561
13.2.1.2 HCIVERSION—Host Controller Interface Version Number
13.2.1.3 HCSPARAMS—Host Controller Structural Parameters .................... 562
13.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register........ 563
13.2.2.1 USB2.0_CMD—USB 2.0 Command Register ................................ 565
13.2.2.2 USB2.0_STS—USB 2.0 Status Register ...................................... 568
13.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ....................... 570
13.2.2.4 FRINDEX—Frame Index Register ............................................... 571
13.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register ........ 572
13.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register .... 572
13.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address Register ..... 573
13.2.2.8 CONFIGFLAG—Configure Flag Register ....................................... 573
13.2.2.9 PORTSC—Port N Status and Control Register .............................. 573
13.2.3.1 CNTL_STS—Control/Status Register .......................................... 577
13.2.3.2 USBPID—USB PIDs Register ..................................................... 580
13.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ......................... 581
13.2.3.4 CONFIG—Configuration Register ............................................... 581
Register................................................................................. 562
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