NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 626
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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16.1.13
16.1.14
626
MBBAR—Bus Master Base Address Register
(Audio—D30:F2)
Address Offset: 1Ch
Default Value:
Lockable:
This BAR creates 256-bytes of memory space to signify the base address of the bus
master memory space. The lower 64-bytes of the space pointed to by this register
point to the same registers as the MBBAR.
SVID—Subsystem Vendor Identification Register
(Audio—D30:F2)
Address Offset: 2Ch
Default Value:
Lockable:
The SVID register, in combination with the Subsystem ID register (D30:F2:2Eh),
enable the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3
31:8
15:0
7:3
2:1
Bit
Bit
0
Base Address — R/W. This field provides the I/O offset to use for decoding the PCM In,
PCM Out, and Microphone 1 DMA engines.
Reserved. Read as 0s.
Type — RO. Hardwired to 00b to indicate the base address exists in 32-bit address
space
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for memory
space.
Subsystem Vendor ID — R/WO.
00000000h
No
0000h
No
–
–
1Fh
2Dh
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
HOT
Description
Description
to D0 transition.
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
R/W, RO
32 bits
Core
R/WO
16 bits
Core
®
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