NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 343
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.25
8.3.26
8.3.27
Intel
®
ICH7 Family Datasheet
PMSK5—Polling Mask 5 Register
(ASF Controller—B1:D8:F0)
Offset Address: FCh
Default Value:
This register provides software an interface for the Polling #5 Data Mask.
PMSK6—Polling Mask 6 Register
(ASF Controller—B1:D8:F0)
Offset Address: FDh
Default Value:
This register provides software an interface for the Polling #6 Data Mask.
PMSK7—Polling Mask 7 Register
(ASF Controller—B1:D8:F0)
Offset Address: FEh
Default Value:
This register provides software an interface for the Polling #7 Data Mask.
7:0
7:0
Bit
Bit
7:0
Bit
Polling Mask for Polling Descriptor #5 (POL5_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #5. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Polling Mask for Polling Descriptor #6 (POL6_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #6. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Polling Mask for Polling Descriptor #7 (POL7_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #7. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
XXh
XXh
XXh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W
8 bits
R/W
8 bits
343
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