NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 163

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.14.7
5.14.7.1
5.14.7.2
Table 5-30. Sleep Types
5.14.7.3
Note:
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ICH7 Family Datasheet
Sleep States
Sleep State Overview
The ICH7 directly supports different sleep states (S1–S5) that are entered by setting
the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based
on several assumptions:
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the
system to a full on state (S0), although some non-critical subsystems might still be
shut off and have to be brought back manually. For example, the hard disk may be shut
off during a sleep state, and have to be enabled via a GPIO pin before it can be used.
Upon exit from the ICH7-controlled Sleep states, the WAK_STS bit is set. The possible
causes of Wake Events (and their restrictions) are shown in
(Mobile/Ultra Mobile Only) If the BATLOW# signal is asserted, ICH7 does not attempt to
wake from an S1–S5 state, even if the power button is pressed. This prevents the
system from waking when the battery power is insufficient to wake the system. Wake
events that occur while BATLOW# is asserted are latched by the ICH7, and the system
wakes after BATLOW# is de-asserted.
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
• Prior to setting the SLP_EN bit, the software turns off processor-controlled
• The G3 state cannot be entered via any software mechanism. The G3 state
• Masking interrupts, turning off all bus master enable bits, setting the desired type
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Sleep
Type
the processor can only perform one register access at a time. A request to Sleep
has higher priority than throttling.
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit disables thermal throttling (since S1–S5 sleep state has higher priority).
indicates a complete loss of power.
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on observing Stop-Grant cycles from the processor or
on clocks other than the RTC clock.
S1
S3
S4
S5
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signal (only supported on desktop platforms). This lowers the processor’s power
consumption. No snooping is possible in this state.
ICH7 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical
circuits. Power is only retained to devices needed to wake from this sleeping state,
as well as to the memory.
ICH7 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to
the memory subsystem. Only devices needed to wake from this state should be
powered.
Same power state as S4. ICH7 asserts SLP_S3#, SLP_S4# and SLP_S5#.
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ICH7 asserts the STPCLK# signal. It also has the option to assert CPUSLP#
Comment
Table
5-31.
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