NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 342

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NH82801GHM S L8YR

Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801GHM S L8YR

Lead Free Status / RoHS Status
Compliant
8.3.22
8.3.23
8.3.24
342
PMSK2—Polling Mask 2 Register
(ASF Controller—B1:D8:F0)
Offset Address: F9h
Default Value:
This register provides software an interface for the Polling #2 Data Mask.
PMSK3—Polling Mask 3 Register
(ASF Controller—B1:D8:F0)
Offset Address: FAh
Default Value:
This register provides software an interface for the Polling #3 Data Mask.
PMSK4—Polling Mask 4 Register
(ASF Controller—B1:D8:F0)
Offset Address: FBh
Default Value:
This register provides software an interface for the Polling #4 Data Mask.
7:0
7:0
7:0
Bit
Bit
Bit
Polling Mask for Polling Descriptor #3 (POL3_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #3. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Polling Mask for Polling Descriptor #4 (POL4_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #4. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Polling Mask for Polling Descriptor #2 (POL2_MSK) — R/W. This field is used to
read and write the data mask for Polling Descriptor #2. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
XXh
XXh
XXh
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
R/W
8 bits
R/W
8 bits
R/W
8 bits
®
ICH7 Family Datasheet

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