NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 715

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.20
19.1.21
Intel
®
ICH7 Family Datasheet
TCSEL—Traffic Class Select Register
(Intel
Address Offset: 44h
Default Value:
This register assigned the value to be placed in the TC field. CORB and RIRB data will
always be assigned TC0.
DCKCTL—Docking Control Register (Mobile Only)
(Intel
Address Offset: 4Ch
Default Value:
7:3
2:0
7:1
Bit
Bit
0
Reserved.
Intel
register assigns the value to be placed in the Traffic Class field for input data, output
data, and buffer descriptor transactions.
000 = TC0
001 = TC1
010 = TC2
011 = TC3
100 = TC4
101 = TC5
110 = TC6
111 = TC7
NOTE: These bits are not reset on D3
Reserved.
Dock Attach (DA) — R/W / RO:
0 = Software writes a 0 to this bit to initiate the undocking sequence on the
1 = Software writes a 1 to this bit to initiate the docking sequence on the
NOTE: Software must check the state of the Dock Mated (GSTS.DM) bit prior to writing
NOTE: This bit is Read Only when the DCKSTS.DS bit = 0.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the undocking sequence is
complete, hardware will set the Dock Mated (GSTS.DM) status bit to 0.
AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the docking sequence is
complete, hardware will set the Dock Mated (GSTS.DM) status bit to 1.
®
PLTRST#.
to the Dock Attach bit. Software shall only change the DA bit from 0 to 1 when
DM=0. Likewise, software shall only change the DA bit from 1 to 0 when DM=1.
If these rules are not followed, the results are undefined.
HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W. This
00h
00h
Description
Description
HOT
Attribute:
Size:
Attribute:
Size:
to D0 transition; however, they are reset by
R/W
8 bits
R/W, RO
8 bits
715