NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 613

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1)
Intel
®
ICH7 Family Datasheet
(Desktop
(Desktop
Mobile
Mobile
Mobile
Mobile
17:16
15:14
(Ultra
(Ultra
Only)
Only)
Only)
Only)
11:8
and
and
3:2
Bit
13
13
12
7
6
5
4
1
1
0
SIG_MODE — R/W. These bits are used to control mode of the IDE signal pins for
mobile/Ultra Mobile swap bay support.
If the PRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of
bits 17:16 will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the ICH7.
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in
conjunction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the
Primary Slave drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this
Reserved
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in
conjunction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the
Primary Master drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the ICH7.
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the ICH7.
Primary Slave Channel Cable Reporting — R/W. BIOS should program this bit to
tell the IDE driver which cable is plugged into the channel.
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
Primary Master Channel Cable Reporting — R/W. Same description as bit 5
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the ICH7.
Primary Drive 1 Base Clock (PCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Reserved
Primary Drive 0 Base Clock (PCB0) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
register).
register).
Description
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