NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 610
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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15.1.21
15.1.22
610
IDE_TIMS — IDE Secondary Timing Register
(IDE—D31:F1)
Address Offset: 42h
Default Value:
SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1) (Desktop and Mobile Only)
Address Offset: 44h
Default Value:
14:12
10:0
7:4
3:2
1:0
Bit
Bit
15
11
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the Intel
Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the
number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point,
if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is
set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the
minimum number of PCI clocks between the last IORDY sample point and the IOR#/
IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE
timing register for primary is set.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
IDE Decode Enable (IDE) — R/W. This bit enables/disables the Secondary decode.
The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be
set in order for this bit to have any effect. Additionally, separate configuration bits are
provided (in the IDE I/O Configuration register) to individually disable the secondary
IDE interface signals, even if the IDE Decode Enable bit is set.
0 = Disable.
1 = Enables the Intel
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the ICH7 since a secondary channel does not
exist.
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the ICH7 since a secondary channel does not
exist.
and Control Block (376h). Accesses to these ranges return 00h, as the secondary
channel is not implemented.
0000h
00h
–
43h
®
ICH7 to decode the associated Command Blocks (170–177h)
®
Description
Description
ICH7.
Attribute:
Size:
Attribute:
Size:
IDE Controller Registers (D31:F1)
Intel
R/W
16 bits
R/W
8 bits
®
ICH7 Family Datasheet
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