NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 679

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.25
Intel
®
ICH7 Family Datasheet
DCTL—Device Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 48h–49h
Default Value:
14:12
7:5
Bit
15
11
10
9
8
4
3
2
1
0
Reserved
Max Read Request Size (MRRS) — RO. Hardwired to 0.
Enable No Snoop (ENS) — RO. Not supported. The root port will not issue non-snoop
requests.
Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device
connected has detected aux power. It has no effect on the root port otherwise.
Phantom Functions Enable (PFE) — RO. Not supported.
Extended Tag Field Enable (ETFE) — RO. Not supported.
Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads,
regardless of the programming of this field.
Enable Relaxed Ordering (ERO) — RO. Not supported.
Unsupported Request Reporting Enable (URE) — R/W.
0 = Disable. The root port will ignore unsupported request errors.
1 = Enable. The root port will generate errors when detecting an unsupported request.
Fatal Error Reporting Enable (FEE) — R/W.
0 = Disable. The root port will ignore fatal errors.
1 = Enable. The root port will generate errors when detecting a fatal error.
Non-Fatal Error Reporting Enable (NFE) — R/W.
0 = Disable. The root port will ignore non-fatal errors.
1 = Enable. The root port will generate errors when detecting a non-fatal error.
Correctable Error Reporting Enable (CEE) — R/W.
0 = Disable. The root port will ignore correctable errors.
1 = Enable. The root port will generate errors when detecting a correctable error.
0000h
Description
Attribute:
Size:
R/W, RO
16 bits
679