NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 813

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
Table 23-22. (Power Sequencing and Reset Signal Timings (Sheet 2 of 2)
Intel
®
ICH7 Family Datasheet
1. 5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after
2. The associated 3.3 V and 1.05 V supplies are assumed to power up or down ‘together’. If the integrated
3. The VccSus supplies must not be active while the VccRTC supply is inactive.
4. (Mobile Only) – a) VccLan3_3 must power up before VccLAN1_05 or after VccLAN1_05 within 0.7 V,
5. (Mobile Only) - Vcc or VccLAN supplies must not be active while the VccSus supplies are inactive, and the Vcc
6. Vcc1_5 must power up before V_CPU_IO or after V_CPU_IO within 0.7 V, b) V_CPU_IO must power down
7. Vcc supplies refer to all “core well” supplies: Vcc3_3, Vcc1_05, Vcc1_5, V5REF, VccUSBPLL, VccDMIPLL,
8. INIT# value determined by value of the CPU BIST Enable bit (Chipset Configuration Register Offset 3414h: bit
9. These transitions are clocked off the internal RTC. 1 RTC clock is approximately from 28.992 µs to 32.044 µs.
NOTES:
Sym
t212
t213
t214
t215
t216
t217
t218
t228
t229
Vcc3_3, or before Vcc3_3 within 0.7 V.
VccSus1_05 voltage regulator is not used: a) VccSus3_3 must power up before VccSus1_05 or after
VccSus1_05 within 0.7 V, b) VccSus1_05 must power down before VccSus3_3 or after VccSus3_3 within 0.7 V.
b) VccLAN1_05 must power down before VccLAN3_3 or after VccLAN3_3 within 0.7V.
supplies must not be active while the VccLAN supplies are inactive.
before Vcc1_5 or after Vcc1_5 within 0.7 V.
VccSATAPLL, V_CPU_IO and VccHDA (Mobile Only). It implies that all “suspend wells” and VccRTC are stable
too.
2).
VccLAN supplies active to Vcc supplies
active
(Mobile Only)
VccSus supplies active to Vcc supplies
active
(Desktop Only)
Vcc supplies active to PWROK
NOTE: PWROK assertion indicates that
V_CPU_IO active to STPCLK# and
CPUSLP# inactive
(Desktop Only)
Vcc active to DPRSLPVR inactive and
STPCLK#, STP_CPU#, STP_PCI#,
DPSLP#, DPRSTP# inactive
(Mobile/Ultra Mobile Only)
PWROK and VRMPWRGD active and
SYS_RESET# inactive to SUS_STAT#
inactive and Processor I/F signals latched
to strap value
SUS_STAT# inactive to PLTRST# inactive
ACZ_RST# active low pulse width
ACZ_RST# inactive to ACZ_BIT_CLK
startup delay
PCICLK has been stable for at
least 1 ms.
Parameter
162.8
Min
99
32
—
—
0
0
2
1
Max
50
50
38
—
—
—
—
—
3
RTCCLK
RTCCLK
Units
ms
ms
ms
ns
ns
us
ns
Notes
5, 7
8, 9
5
3
9
23-19
23-18
23-18
23-19
23-20
23-21
23-23
23-24
23-25
23-26
23-20
23-23
23-24
23-21
23-25
23-26
23-20
23-21
23-23
23-24
23-25
23-26
23-20
23-21
23-23
23-24
23-25
23-26
Fig
813