NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 595

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
14.2.9
14.2.10
.
14.2.11
.
Intel
®
ICH7 Family Datasheet
RCV_SLVA—Receive Slave Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 09h
Default Value:
Lockable:
SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Ah–0Bh
Default Value:
Lockable:
This register contains the 16-bit data value written by the external SMBus master. The
processor can then read the value from this register. This register is reset by RSMRST#,
but not PLTRST#
AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Ch
Default Value:
Lockable:
15:8
6:0
7:0
7:2
Bit
Bit
Bit
7
1
0
Reserved
SLAVE_ADDR — R/W. This field is the slave address that the Intel
read and write cycles. the default is not 0, so the SMBus Slave Interface can respond
even before the processor comes up (or if the processor is dead). This register is
cleared by RSMRST#, but not by PLTRST#.
Data Message Byte 1 (DATA_MSG1) — RO. See
this field.
this field.
Reserved
SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible
mode vs. Advanced TCO mode.
0 = Intel
1 = ICH7 is in the advanced TCO mode.
CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the
Data Message Byte 0 (DATA_MSG0) — RO. See
DERR bit of the host status register will also be set. This bit will be set by the
controller if a software abort occurs in the middle of the CRC portion of the cycle or
an abort happens after the ICH7 has received the final data bit transmitted by an
external slave.
®
44h
No
0000h
No
00h
No
ICH7 is in the compatible TCO mode.
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Section 5.21.7
Section 5.21.7
R/W
8 bits
Resume
RO
16 bits
Resume
R/WC, RO
8 bits
Resume
®
for a discussion of
for a discussion of
ICH7 decodes for
595