NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 657
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
17.2.1
17.2.2
17.2.3
Intel
®
ICH7 Family Datasheet
x_BDBAR—Buffer Descriptor List Base Address Register
(Modem—D30:F3)
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single, 32-bit read from
address offset 00h. Reads across DWord boundaries are not supported.
x_CIV—Current Index Value Register (Modem—D30:F3)
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software can also read this
register individually by doing a single, 8-bit read to offset 04h. Reads across DWord
boundaries are not supported.
x_LVI—Last Valid Index Register (Modem—D30:F3)
I/O Address:
Default Value:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software can also read this
register individually by doing a single, 8-bit read to offset 05h. Reads across DWord
boundaries are not supported.
31:3
2:0
7:5
4:0
7:5
4:0
Bit
Bit
Bit
Hardwired to 0.
Current Index Value [4:0] — RO. These bits represent which buffer descriptor
within the list of 16 descriptors is being processed currently. As each descriptor is
processed, this value is incremented.
Hardwired to 0
Last Valid Index [4:0] — R/W. These bits indicate the last valid descriptor in the list.
This value is updated by the software as it prepares new buffers and adds to the list.
Buffer Descriptor List Base Address [31:3] — R/W. These bits represent address
bits 31:3. The entries should be aligned on 8-byte boundaries.
Hardwired to 0.
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
00000000h
No
MBAR + 04h (MICIV),
MBAR + 14h (MOCIV),
00h
No
MBAR + 05h (MILVI),
MBAR + 15h (MOLVI)
00h
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Power Well:
R/W
32bits
Core
RO
8bits
Core
R/W
Core
657
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