NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 282

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

7.1.40
282
TCTL—TCO Configuration Register
Offset Address: 3000–3000h
Default Value:
6:3
2:0
Bit
7
TCO IRQ Enable (IE) — R/W.
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
Reserved
TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear.
If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that
interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI
interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and
can be shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
011 = Reserved
100 = IRQ 20 (only if APIC enabled)
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
NOTE: When setting the these bits, the IE bit should be cleared to prevent glitching.
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should
be programmed for active-high reception. When the interrupt is mapped to
APIC interrupts 20 through 23, the APIC should be programmed for active-
low reception.
00h
Description
Size:
Attribute:
Chipset Configuration Registers
Intel
R/W
8-bit
®
ICH7 Family Datasheet