NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 294

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

7.1.51
294
OIC—Other Interrupt Control Register
Offset Address: 31FF–31FFh
Default Value:
6:4
2:0
7:2
Bit
Bit
3
1
0
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTB# pin reported for device 27 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
Reserved
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 27 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
Reserved
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
I/O port F0h write. It will also drive IGNNE# active.
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
00h
®
ICH7 generates IRQ13 internally and holds it until an
Description
Description
Attribute:
Size:
Chipset Configuration Registers
Intel
R/W
8-bit
®
ICH7 Family Datasheet